Modern day metal-oxide-semiconductor field-effect transistors (MOSFET) typically utilize gates made of polysilicon. One disadvantage in utilizing polysilicon gates for MOSFETs is the depletion effect that affects polysilicon gates. At inversion, a polysilicon gate generally experiences depletion of carriers in the area of the polysilicon adjacent the gate dielectric. The depletion effect reduces the effective gate capacitance of the MOSFET incorporating a polysilicon gate. Ideally, it is desirable that the gate capacitance is high. The higher the gate capacitance, the more charge is accumulated on both sides of the gate capacitor, and therefore more charge is accumulated in the channel. As more charge is accumulated in the channel, the drain-source current becomes higher when the transistor is biased.
FIG. 1 illustrates, in simplified form, a cross-sectional view of a MOSFET that has a polysilicon gate electrode 8. Due to the polysilicon material of gate electrode 8, the depletion effect causes charged carriers to accumulate near interface 4 between gate electrode 8 and the gate dielectric 2. Accordingly, the effective gate capacitance decreases. This is due to an increase in the effective distance between the charges accumulated on both sides of the gate dielectric 2. The effective distance that separates the charge on both sides of gate dielectric 2 becomes larger due to the depletion of charge, in the polysilicon gate 8, in the vicinity of interface 4. Accordingly, polysilicon gate electrode 8 causes the effective gate capacitance to decrease.
Silicide metal gates have been proposed as a promising replacement for polysilicon gates for MOS transistors. FIG. 2 illustrates a cross-sectional view of a MOSFET with a silicided polysilicon gate. The gate has a layer of silicide 10 with an underlying layer of polysilicon 8. Polysilicon 8 typically exists because of under silicidation. While silicide 10 may help decrease the resistance of the gate, charge is still depleted in the vicinity of interface 4 between polysilicon 8 and gate oxide 2, thereby causing a smaller effective gate capacitance.
Fully silicide gates were developed to solve the above-mentioned problem. Like pure metals, fully silicided gates eliminate the gate-depletion effect. Fully silicided gates are formed by a two-step process. First, silicide is formed in the source/drain region, and the hard-mask prevents silicide formation on gate. After a liner oxide or nitride deposition, the gate is subject to a CMP process to expose the gate polysilicon. A second silicide is formed on gate resulting in silicide metal gate.
The conventional formation process of metal silicide gates has some disadvantages. Incomplete gate silicidation and variations in the gate silicide phase are serious challenges. Non-uniform silicidation will impact on device work function, threshold voltage, equivalent oxide thickness, gate leakage, and gate resistance. FIG. 3 illustrates an example of the silicidation variation. MOS transistors 11 and 13 are formed in separated regions having different device density. Due to CMP variations, the thickness of the gate electrodes 14 and 16 are different. During the silicide, the thick difference Hv causes either over silicidation or under silicidation. A small device may be silicided fully, but a large device based on the same condition may not. The gate difference may also come from nMOS and pMOS. For example, using the same process, an nMOS gate has a thickness of about 210 Å, and a pMOS has a thickness of about 530 Å. The thickness difference comes from the different poly doping type. This poly thickness difference is too high for the silicidation process applied to nMOS and pMOS at the same time. Another silicidation variation occurs at wafer level. After poly gate etch back, there may be about 100 Å poly height difference between devices at the wafer center and wafer edge.
Besides the silicidation variations, the traditional two-step fully silicided gate process is complicated, increasing cost and decreasing yield. Therefore, new method for forming fully silicided gates is needed.